/**
 * MIT License
 * 
 * Copyright (c) 2024 - present @ ebraid
 * 
 * Email: 1477153217@qq.com
 * QQ: 1477153217
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __EB_SUNIV_H__
#define __EB_SUNIV_H__


#define         DRAM_BASE       	             (0x01c01000)
#define         DRAM_SCONR			             (0x00)
#define         DRAM_STMG0R			             (0x04)
#define         DRAM_STMG1R			             (0x08)
#define         DRAM_SCTLR			             (0x0c)
#define         DRAM_SREFR			             (0x10)
#define         DRAM_SEXTMR			             (0x14)
#define         DRAM_DDLYR			             (0x24)
#define         DRAM_DADRR			             (0x28)
#define         DRAM_DVALR			             (0x2c)
#define         DRAM_DRPTR0			             (0x30)
#define         DRAM_DRPTR1			             (0x34)
#define         DRAM_DRPTR2			             (0x38)
#define         DRAM_DRPTR3			             (0x3c)
#define         DRAM_SEFR			             (0x40)
#define         DRAM_MAE			             (0x44)
#define         DRAM_ASPR			             (0x48)
#define         DRAM_SDLY0			             (0x4C)
#define         DRAM_SDLY1			             (0x50)
#define         DRAM_SDLY2			             (0x54)
#define         DRAM_MCR0			             (0x100)
#define         DRAM_MCR1			             (0x104)
#define         DRAM_MCR2			             (0x108)
#define         DRAM_MCR3			             (0x10c)
#define         DRAM_MCR4			             (0x110)
#define         DRAM_MCR5			             (0x114)
#define         DRAM_MCR6			             (0x118)
#define         DRAM_MCR7			             (0x11c)
#define         DRAM_MCR8			             (0x120)
#define         DRAM_MCR9			             (0x124)
#define         DRAM_MCR10			             (0x128)
#define         DRAM_MCR11			             (0x12c)
#define         DRAM_BWCR			             (0x140)

#define         CCU_BASE		                 (0x01c20000)
#define         CCU_PLL_CPU_CTRL		         (0x000)
#define         CCU_PLL_AUDIO_CTRL		         (0x008)
#define         CCU_PLL_VIDEO_CTRL		         (0x010)
#define         CCU_PLL_VE_CTRL			         (0x018)
#define         CCU_PLL_DDR_CTRL		         (0x020)
#define         CCU_PLL_PERIPH_CTRL		         (0x028)
#define         CCU_CPU_CFG				         (0x050)
#define         CCU_AHB_APB_CFG			         (0x054)

#define         CCU_BUS_CLK_GATE0		         (0x060)
#define         CCU_BUS_CLK_GATE1		         (0x064)
#define         CCU_BUS_CLK_GATE2		         (0x068)

#define         CCU_SDMMC0_CLK			         (0x088)
#define         CCU_SDMMC1_CLK			         (0x08c)
#define         CCU_DAUDIO_CLK			         (0x0b0)
#define         CCU_SPDIF_CLK			         (0x0b4)
#define         CCU_I2S_CLK				         (0x0b8)
#define         CCU_USBPHY_CFG			         (0x0cc)
#define         CCU_DRAM_CLK_GATE		         (0x100)
#define         CCU_DEBE_CLK			         (0x104)
#define         CCU_DEFE_CLK			         (0x10c)
#define         CCU_LCD_CLK				         (0x118)
#define         CCU_DEINTERLACE_CLK		         (0x11c)
#define         CCU_TVE_CLK				         (0x120)
#define         CCU_TVD_CLK				         (0x124)
#define         CCU_CSI_CLK				         (0x134)
#define         CCU_VE_CLK				         (0x13c)
#define         CCU_ADDA_CLK			         (0x140)
#define         CCU_AVS_CLK				         (0x144)
         
#define         CCU_PLL_STABLE_TIME0	         (0x200)
#define         CCU_PLL_STABLE_TIME1	         (0x204)
#define         CCU_PLL_CPU_BIAS		         (0x220)
#define         CCU_PLL_AUDIO_BIAS		         (0x224)
#define         CCU_PLL_VIDEO_BIAS		         (0x228)
#define         CCU_PLL_VE_BIAS			         (0x22c)
#define         CCU_PLL_DDR0_BIAS		         (0x230)
#define         CCU_PLL_PERIPH_BIAS		         (0x234)
#define         CCU_PLL_CPU_TUN			         (0x250)
#define         CCU_PLL_DDR_TUN			         (0x260)
#define         CCU_PLL_AUDIO_PAT		         (0x284)
#define         CCU_PLL_VIDEO_PAT		         (0x288)
#define         CCU_PLL_DDR0_PAT		         (0x290)
#define         CCU_BUS_SOFT_RST0		         (0x2c0)
#define         CCU_BUS_SOFT_RST1		         (0x2c4)
#define         CCU_BUS_SOFT_RST3		         (0x2d0)


#define         PLL_CPU                           CCU_PLL_CPU_CTRL
#define         PLL_AUDIO                         CCU_PLL_AUDIO_CTRL
#define         PLL_VIDEO                         CCU_PLL_VIDEO_CTRL
#define         PLL_VE                            CCU_PLL_VE_CTRL
#define         PLL_DDR                           CCU_PLL_DDR_CTRL
#define         PLL_PERIPH                        CCU_PLL_PERIPH_CTRL


#define         CLK_CPU_SRC_LOSC                  0
#define         CLK_CPU_SRC_OSC24M                1
#define         CLK_CPU_SRC_PLL_CPU               2


#define         RESET_DMA			             (6)
#define         RESET_SD0			             (8)
#define         RESET_SD1			             (9)
#define         RESET_SDRAM			             (14)
#define         RESET_SPI0			             (20)
#define         RESET_SPI1			             (21)
#define         RESET_USB_OTG		             (24)
#define         RESET_VE			             (32)
#define         RESET_LCD			             (36)
#define         RESET_DEINTERLACE	             (37)
#define         RESET_CSI			             (40)
#define         RESET_TVD			             (41)
#define         RESET_TVE			             (42)
#define         RESET_DEBE			             (44)
#define         RESET_DEFE			             (46)
#define         RESET_ADDA			             (64)
#define         RESET_SPDIF			             (65)
#define         RESET_CIR			             (66)
#define         RESET_RSB			             (67)
#define         RESET_DAUDIO		             (76)
#define         RESET_I2C0			             (80)
#define         RESET_I2C1			             (81)
#define         RESET_I2C2			             (82)
#define         RESET_UART0			             (84)
#define         RESET_UART1			             (85)
#define         RESET_UART2			             (86)


#define         SRAMC_REG_BASE                   (0x01C00000)
#define         DRAMC_REG_BASE                   (0x01C01000)
#define         DMA_REG_BASE                     (0x01C02000)
#define         SPI0_REG_BASE                    (0x01C05000)
#define         SPI1_REG_BASE                    (0x01C06000)
#define         TVE_REG_BASE                     (0x01C0A000)
#define         TVD_REG_BASE                     (0x01C0B000)
#define         TCON_REG_BASE                    (0x01C0C000)
#define         VE_REG_BASE                      (0x01C0E000)
#define         SDC0_REG_BASE                    (0x01C0F000)
#define         SDC1_REG_BASE                    (0x01C10000)
#define         USB_REG_BASE                     (0x01C13000)
#define         CCU_REG_BASE                     (0x01C20000)
#define         INTC_REG_BASE                    (0x01C20400)
#define         GPIO_REG_BASE                    (0x01C20800)
#define         TIMER_REG_BASE                   (0x01C20C00)
#define         PWM_REG_BASE                     (0x01C21000)
#define         OWA_REG_BASE                     (0x01C21400)
#define         RSB_REG_BASE                     (0x01C21800)
#define         I2S_REG_BASE                     (0x01C22000)
#define         CIR_REG_BASE                     (0x01C22C00)
#define         KEYADC_REG_BASE                  (0x01C23400)
#define         CODEC_REG_BASE                   (0x01C23C00)
#define         RTP_REG_BASE                     (0x01C24800)
#define         UART0_REG_BASE                   (0x01C25000)
#define         UART1_REG_BASE                   (0x01C25400)
#define         UART2_REG_BASE                   (0x01C25800)
#define         I2C0_REG_BASE                    (0x01C27000)
#define         I2C1_REG_BASE                    (0x01C27400)
#define         I2C2_REG_BASE                    (0x01C27800)
#define         CAMERA_REG_BASE                  (0x01CB0000)
#define         DEFE_REG_BASE                    (0x01E00000)
#define         DEBE_REG_BASE                    (0x01E60000)
#define         DEIN_REG_BASE                    (0x01E70000)


#endif // __EB_SUNIV_H__